NextSilicon’s Maverick-2 Dataflow Engine Redefines HPC Computing Paradigm

Revolutionary Architecture Challenges Traditional Computing

After eight years of development and $303 million in funding, NextSilicon has officially launched its Maverick-2 dataflow engine, representing a fundamental shift in high-performance computing architecture. The company’s approach directly confronts the limitations of conventional CPUs and GPUs by reimagining how computational resources are allocated and utilized.

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The Intelligent Computing Architecture Difference

NextSilicon’s breakthrough lies in what they term Intelligent Computing Architecture (ICA), which fundamentally reallocates silicon resources from control overhead to actual computation. According to Ilan Tayari, NextSilicon’s co-founder and vice president of architecture, traditional CPUs dedicate only about 2% of their silicon to arithmetic logic units (ALUs) – the components that actually perform mathematical operations. The remaining 98% serves as support infrastructure for instruction and data management.

“Today’s high-end processors have become complicated and chunky, both physically and practically,” Tayari explained during the Maverick-2 launch. “They dedicate 98 percent of their silicon to overhead, traffic management, data shuffling – not actual computation.”

Maverick-2 Technical Specifications

The Maverick-2 chip represents a monumental engineering achievement with several key features:, according to related coverage

• 54 billion transistors manufactured using TSMC’s 5nm process
• 224 compute blocks arranged in a grid of seven columns with eight blocks each
• 32 RISC-V E-cores positioned along the chip’s edges
• Potential for tens of thousands to nearly 100,000 ALUs across the chip
• Operating frequency of 1.5 GHz with support for HBM3E memory

Dataflow Engine vs Von Neumann Architecture

The core innovation separates NextSilicon from traditional computing approaches. While conventional CPUs follow the Von Neumann architecture developed in the 1940s – featuring a unified memory space for instructions and data with complex prediction and execution circuits – Maverick-2 implements a true dataflow architecture.

“With a dataflow engine such as NextSilicon has invented, the hardware literally maps itself to the software,” the company explains. This approach eliminates the need for branch prediction, speculative execution, and out-of-order processing that consume significant resources in traditional processors.

Mill Cores and Thread Management

NextSilicon’s architecture introduces “mill cores” – configurable computational units that can support hundreds of threads simultaneously. With potentially thousands of mill cores active across the chip’s 224 compute blocks, the Maverick-2 can maintain exceptionally high utilization rates for ALUs and floating-point units., as our earlier report, according to additional coverage

Elad Raz, NextSilicon’s co-founder and CEO, notes that “mill cores can be loaded up and deleted as needed in a matter of nanoseconds” according to workload demands, enabling dynamic resource allocation that traditional architectures cannot match.

Software Compatibility and Deployment

Perhaps most impressively, NextSilicon’s technology doesn’t require developers to learn new programming languages. Existing C, C++, and Fortran code can be compiled for the dataflow engine, with the intermediate representation directly mapped onto the ALU blocks. This approach significantly lowers the barrier to adoption for HPC centers considering the technology.

Sandia National Laboratory, which assisted with development of the Maverick-1 proof of concept, is expected to be among the first production deployments of Maverick-2 systems. The architecture’s focus on 64-bit floating point computing makes it particularly appealing for scientific computing and traditional HPC workloads, though the company notes nothing prevents running AI applications on the processor.

Industry Implications

NextSilicon’s emergence as an HPC-first company marks a significant departure from the general-purpose computing trend that has dominated the industry. By focusing specifically on high-performance computing needs and optimizing for computational efficiency rather than general versatility, Maverick-2 could potentially deliver substantial performance per watt improvements for specialized workloads.

The combination of Maverick-2 with NextSilicon’s homegrown RISC-V processor, Arbel, creates what the company describes as a “superchip” host-accelerator combination, offering a genuinely novel alternative to current CPU-GPU architectures for the world’s most demanding computational challenges.

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